A. Field of the Invention
This invention relates to the field of digital data processing systems wherein one or more host data processors utilize one or more supporting Scientific Processors in conjunction with storage systems that are commonly accessible. More particularly it relates to an improved High Performance Storage Unit for use in such a digital data processing system. Still more particularly, it relates to an improved pipelined stack that utilizes at least two groupings of Stack Registers with High Performance Interleaved Decoding of access to the groups of Stack Registers to enhance the rate of stack operation.
B. State of the Prior Art
Digital data processing systems are known wherein one or more independently operable data processors function with one or more commonly accessible main storage systems. Systems are also known that utilize a support processor with its associated dedicated supporting, or secondary storage system. Such support processors are often configured to perform specialized scientific computations and are commonly under task assignment control of one of the independently operable data processors. The controlling data processor is commonly referred to as a "host processor". The host processor characteristically functions to cause a task to be assigned to the support processor; to cause required instructions and data to be transferred to the secondary storage system; to cause the task execution to be initiated; and to respond to signals indicating the task has been completed, so that results can be transferred to the selected main storage systems. It is also the duty of the host processor to recognize and accommodate conflicts in usage and timing that might be detected to exist. Commonly, the host processor is free to perform other data processing matters while the support processor is performing its assigned tasks. It is also common for the host processor to respond to intermediate needs of the support processor, such as providing additional data if required, responding to detected fault conditions and the like.
In the past, support scientific data processors have been associated with host data processing systems. One such prior art scientific processor is disclosed in U.S. Pat. No. 4,101,960, entitled "Scientific Processor" and assigned to Burroughs Corporation, of Detroit, Mich. In that system, a single instruction multiple data processor, which is particularly suited for scientific applications, includes a high level language programmable front-end processor; a parallel task processor with an array memory; a large high speed secondary storage system having a multiplicity of high speed input/output channels commonly coupled to the front-end processor and to the array memory; and an over-all control unit. In operation of that system, an entire task is transferred from the front-end processor to the secondary storage system whereupon the task is thereafter executed on the parallel task processor under the supervision of the control unit, thereby freeing the front-end processor to perform general purpose input/output operations and other tasks. Upon parallel task completion, the complete results are transferred back to the front-end processor from the secondary storage system.
It is believed readily seen that the front-end processor used in this earlier system is a large general purpose data processing system which has its own primary storage system. It is from this primary storage system that the entire task is transferred to the secondary storage system. Further, it is believed to be apparent that an input/output path exists to and from the secondary storage system from this front-end processor. Since task transfers involve the use of the input/output path of the front-end processor, it is this input/output path and the transfer of data thereon between the primary and secondary storage systems which becomes the limiting link between the systems. Such a limitation is not unique to the Scientific Processor as disclosed in U.S. Pat. No. 4,101,960. Rather, this input/output path and the transfers of data are generally considered to be the bottleneck in many such earlier known systems.
The present scientific data processing system is considered to overcome the data transfer bottleneck by providing a unique system architecture using a high speed memory unit which is commonly accessible by the host processor and the scientific processor. Further, when multiple high speed storage units are required, a multiple unit adapter is coupled between a plurality of high speed memory units and the scientific processor.
Data processing systems are becoming more and more complex. With the advent of integrated circuit fabrication technology, the cost per gate of logic elements is greatly reduced and the number of gates utilized is ever-increasing. A primary goal in architectural design is to improve the through-put of problem solutions. Such architectures often utilize a plurality of processing units in cooperation with one or more multiple port memory systems, whereby portions of the same problem solution may be parcelled out to different processors or different problems may be in the process of solution simultaneously.
When a Scientific Processor (SP) is utilized in a data processing system to perform supporting scientific calculations in support of a host processor or processors, and is utilized in conjunction with two or more High Performance Storage Units (HPSU's), the problem of timing of access of the SP to any selected HPSU for either reading or writing causes problems of access coordination. In order to coordinate and provide the required control, the over-all system is arbitrarily bounded to require that the SP issue no more than a predetermined number of Requests for access without the receipt back of an Acknowledge. In one configuration, the system is bounded by requiring that no more than eight such Requests be issued by the SP without receipt of an Acknowledge. The details of the interface and control of a Multiple Unit Adapter for transmitting data to and from a designated HPSU by the SP is described in detail in the co-pending application entitled "Multiple Unit Adapter". There it is pointed out that the interface to the HPSU's must also provide for and accommodate different requesters that may be associated therewith. While the data processing system is essentially synchronous, that is operations are under clock control in their execution, the occurrence of Requests, the availability of responding units, and the occurrence of Acknowledge signals are asynchronous with respect to each other. The details of operation of the HPSU's are set forth in detail in the co-pending application entitled "High Performance Storage Unit".
The prior art has recognized the advantageous operation of utilizing buffers to match transmissions between two operating systems that have different operational rates. As so-called pipelined architectures were developed to improve the rates of through put, the concept of buffering was extended to the development of intermediate stack structures for temporarily storing or holding data items pending availability of the destination unit. Early versions of stacks of this type involved a first-in first-out (FIFO) structural arrangement with control that would cause Requests and data to be shifted through the stack shift registers such that the first Request and its associated data would be processed first and then on in order as they occurred. This type of shift register stack requires the control to cause shifting through the registers as Acknowledges are received, together with control to determine when the stack is full and no more Requests can be received. Shifting stacks are relatively slow, consume unnecessary power, and require an undue amount of circuitry to implement.
The problems with shift register stacks have been addressed and various configurations of virtual FIFO stacks have been developed. In virtual FIFO stacks data words are stored in registers controlled by loading identifiers. The data words once stored remain in the associated stack register until accessed for readout, and do not shift from register to register. Instead, the shifting of readout is directed and controlled by readout control signals. In operation, then, when data is to be loaded or written in the stack, the Load Pointer (Load PTR) or Write Pointer (Write PTR) is advanced for each write operation. Similarly, for each read operation the Read Pointer (Read PTR) is advanced. When appropriately controlled, the Pointers sequence circularly through the stack registers at all times providing a FIFO function. By thus controlling the Pointers, it is unnecessary to shift the data from stack register to stack register. When no data is stored in the stack, the two Pointer would reference the same stack register address. The difference between the Load PTR and Read PTR indicates the number of words in the buffer stack. When the Pointers are binary numbers the difference is a numerical count.
It is of course apparent that since the virtual FIFO stack is functionally circular, external control must be exercised in applying Requests to read and write to avoid over-writing. Accordingly, such virtual stacks are also normally bounded to accommodate a predetermined number of load Requests that can occur without having received an Acknowledge that results from reading out a register from the stack.
Virtual FIFO stacks are described in the identified co-pending applications, and have been described in technical literature.
Various other types of virtual stack structures have been described, for example where a virtual FIFO buffer can accommodate variable numbers of data words, and where synchronization is dynamically adjusted depending upon the rate of transfer through the FIFO buffer. An example of the latter type of FIFO buffer is described in U.S. Pat. No. 4,288,860, entitled "Dynamic Storage Synchronizer Using Variable Oscillator" issued to John R. Trost and assigned to the assignee of the subject invention.
In order for a High Performance Storage Unit (HPSU) to operate at a first interface data rate with host processors, and to operate at a second substantially faster interface data rate with associated Scientific Processors, it was found that pipelined stack structures of the type known in the prior art were inadequate. In a preferred embodiment where the host processor interface rate is two parallel memory words at 60 nanoseconds, and the SP interface is four parallel memory words at 30 nanoseconds, it became clear that the serial time to manipulate the Read PTR, to accomplish the readout of the address information and to decode and issue a Bank Request to the selected one of the plurality of Memory Banks in the system was too long. The specific bit configuration for accessing and addressing the various Memory Banks in the HPSU are described in the identified related patent applications, and in particular in the application entitled "High Performance Storage Unit."